1. Field of the Invention
The present invention relates to a three-dimensional multichip module (MCM) and a semiconductor chip which can be used in this MCM. More particularly, the present invention relates to a technique for designing and manufacturing a semiconductor chip, such as a standard cell and an embedded array which can be used in an MCM, using computer-aided design (CAD). Further, the present invention relates to a storage medium for storing data used when design using CAD is carried out.
2. Description of the Related Art
Gate array, standard cell and embedded array are conventionally known methods for efficiently designing a semicustom LSI, as means for designing an Application Specific Integrated circuit (ASIC), which simply realizes a device for specific application using CAD.
A gate array is formed by preparing a master wafer beforehand, having transistors laid thereon in an array, and adding interconnections to the master wafer so as to produce a logic system. As shown in the example of FIG. 1, bonding pads (I/O pads) 101 are provided at the peripheral region of a chip, and a random logic block 102 is provided in the remaining region (central region) of the chip. In the random logic block 102, transistors are laid in an array.
However, a gate array architecture cannot be used to realize a large-scale macrocell such as a CPU or a memory. For this reason, a standard cell design methodology was introduced to simply realize a large-scale macrocell. To produce a standard cell, optimally designed and verified macrocells, registered beforehand in a CAD design database, are assembled in a predetermined layout using CAD. As shown in the example of FIG. 2, bonding pads 201 are provided at the peripheral region of the chip, and macrocells, comprising a CPU core 202, a RAM 203, a RAMBUS interface 204, a PLL 205 and a ROM 206, are provided in central region of the chip. These macrocells are directly connected to each other by interconnections.
The standard cell architecture enables large-scale macrocells to be formed easily, but has a disadvantage that the fabrication of each macrocell must start from the transistor unit level, or from the beginning of the fabrication process, lengthening development time.
Therefore, an embedded array architecture, in which standard cell macrocells are buried in the random logic block of a gate array, has been proposed.
This embedded array is manufactured after the number of gates and the types of macrocells to be contained within the random logic block have been decided. In other words, the embedded array is customised after the wafer process has been commenced but prior to the metallization process. In this state, completion of the logic design is awaited and, after a logic simulation has been carried out, the embedded array is completed by providing interconnections to the random logic block. As shown in the example of FIG. 3, bonding pads 301 are provided at the peripheral region of the chip, and macrocells comprising a CPU core 302, a RAM 303, a RAMBUS interface 304, a PLL 305 and a ROM 306, are provided in central region of the chip. In addition, a random logic block 307 is provided in order to realize the functions of these macrocells.
This embedded array comprises the random logic block, and therefore the customization of the embedded array do not need to be started from the transistor unit level. Consequently, time needed to develop the standard cell can be reduced. Moreover, changes to the circuits of the random logic block can dealt with simply by changing the interconnections.
However, on the conventional embedded array or the standard cell, no bump pads are prepared as the components of the cells for connecting to another chip directly above or below the embedded array or the standard cell. Then, when assembling an MCM with a chip fabricated by the conventional embedded array or the standard cell approach in combination with another pre-existing chip, these chips must be disposed in a side-by-side configuration, or two-dimensional configuration as shown in FIG. 4A and FIG. 4B.
FIG. 4A is a top view, and FIG. 4B, a side view. As shown in FIG. 4A and FIG. 4B, a chip 401 and a chip 402 are provided on a lead frame 400. Chip 401 is the conventional embedded array or the standard cell, and chip 402 is the pre-existing chip. Since it is not possible to stack the chips 401 and 402 three-dimensionally one above the other, they are arranged side by side on the lead frame 400. Then the right side bonding pads 403 on chip 401, and the left side bonding pads 404 on chip 402 are connected by bonding wires 407. And the left side bonding pads 403 on chip 401 and leads 406 are connected by bonding wires 405. Further, the right side bonding pads 404 on the chip 402 and leads 409 are connected by bonding wires 408.
The above structure, wherein multiple chips are two-dimensionally provided side by side, makes it impossible to reduce the area of the frame to less than the total area of the chips. As a result, the mounting area of the package cannot be made small.
Furthermore, the conventional MCM has a problem that electrical signals exchanged between the chips are delayed due to the long distance of the interconnections between the chips. As a consequence, it has been difficult to achieve high-speed executions with the conventional MCM. Furthermore, in a two-dimensional chip structure, it has been difficult to reduce noise generated by electrical signals exchanged between the chips.
The present invention has been achieved in order to solve the conventional problems described above and aims to provide a MCM of smaller scale.
It is another object of the present invention to provide a three-dimensional MCM using an ASIC, such as a standard cell or an embedded array, as a base chip.
It is yet another object of the present invention to provide a three-dimensional MCM wherein distance of interconnections between chips is short, delay of electrical signals exchanged between the chips is reduced, and high-speed behaviour is achieved.
It is yet another object of the present invention to provide a three-dimensional MCM in which noise generation of electrical signals exchanged between the chips is reduced.
It is yet another object of the present invention to provide an ASIC, such as a high general versatility standard cell or embedded array, which can be easily assembled in a three-dimensional MCM.
It is yet another object of the present invention to provide a manufacturing method whereby a small-scale high-speed high-performance three-dimensional MCM, which uses a standard cell as the base chip, can be easily designed and manufactured.
It is yet another object of the present invention to provide a manufacturing method whereby a small-scale high-speed high-performance three-dimensional MCM, which uses an embedded array as the base chip, can be easily designed and manufactured.
It is yet another object of the present invention to provide a storage medium for storing data needed for designing layout and the like of a macrocell, a bump pad and interconnections, and to easily and quickly manufacture a three-dimensional MCM which uses a standard cell as a base chip.
It is yet another object of the present invention to provide a storage medium for storing data needed for designing layout and the like of a macrocells, a random logic block and a bump pad, and to easily and quickly manufacture a three-dimensional MCM which uses an embedded array as a base chip.
In order to achieve the above objects, a multichip module (MCM) comprising a three-dimensional structure, wherein a base chip and an external chip are connected by a bump, constitutes a first aspect. In other words, the first aspect of the present invention is an MCM comprising: a base chip having: a bonding pad provided at a peripheral region thereof; an internal circuit containing macrocells provided in and at proximity to a central region of the base chip; and a bump pad provided at proximity to the central region except over the internal circuit; a bump provided on the bump pad; and an external chip to be attached three-dimensionally with the base chip via the bump.
According to the first aspect of the present invention, a base chip, comprising an IC such as a standard cell or an embedded array, can be easily electrically connected to an external chip, enabling the package to be made small-scale. The silicon on silicon-type MCM of the first aspect of the present invention enables the distance of interconnections between the chips to be shortened and reduces delay of signals exchanged between the chips. As a consequence, high-speed performances can be achieved. Furthermore, it is possible to reduce noise generated by the exchange of signals between the chips.
A second aspect of the present invention relates to a base chip which can be used in the MCM according to the first aspect. In other words, the second aspect of the present invention comprises a base chip having a bonding pad provided at a peripheral region of the base chip; an internal circuit containing macrocells provided in and at proximity to a central region of the base chip; and a bump pad provided at proximity to the central region except above the internal circuit. Can be used in the MCMxe2x80x2 means the base chip can be used as a single unit depending on design specifications.
By using the base chip of the second aspect of the present invention, when designing a system it is possible to freely select whether to three-dimensionally assemble the base chip with an external chip so as to form an MCM, or to use the base chip as a single unit. Particularly, when the base chip is assembled in an MCM, the scale of the package can be made smaller than a two-dimensional package. When assembled as a silicon on silicon-type MCM, the distance of interconnections between the chips can be shortened and delay of signals exchanged between the chips can be reduced. Consequently, high-speed performances can be achieved. Furthermore, it is possible to reduce noise generated by the exchange of signals between the chips. Since the base chip can be freely used as a single unit or assembled as an MCM, general versatility is higher.
A third aspect of the present invention provides a method for manufacturing a three-dimensional MCM comprising the steps of preparing and storing macrocell cell information and said bump pad cell information, logic designing, designing layout, fabricating a mask pattern, fabricating a standard cell and assembling. Here, in the step of logic designing, a standard cell, comprising verified macrocells based on a system specification defining various design conditions relating to the standard cell, is logically designed. In the step of designing layout, the layout of the macrocells, bump pads and interconnections on a basechip are designed using the result of the logic design, the cell information of the macrocell and the bump pad. In the step of fabricating a mask pattern, a mask pattern is made based on the result of the step of designing layout. In the step of fabricating the standard cell, the standard cell is fabricated on the basechip using the mask pattern. And, in the step of assembling, an external chip and the basechip are three-dimensionally assembled via bumps provided on the bump pads, thereby connecting the external chip to the basechip.
According to the third aspect, a standard cell which can be used as a base chip in a silicon on silicon-type MCM can be easily designed and manufactured. Therefore, an MCM using the standard cell can be easily manufactured.
A fourth aspect of the present invention provides a method for manufacturing a three-dimensional MCM comprising the steps of preparing a system specification, preparing cell information of a bump pad capable of directly connecting a embedded array to an external chip to be stacked in a vertical direction, logic designing, designing layout, fabricating a mask pattern for a master wafer, fabricating a master wafer, designing interconnections, fabricating a metallization mask pattern, metallizing and assembling. Here, the system specification defines various design conditions relating to the embedded array having verified macrocells and a random logic block for realizing functions of the macrocells. In the step of logic designing, an embedded array is logically designed based on the system specification and the cell information. In the step of designing layout, layout is designed of at least the macrocell, the random logic block and the bump pad, at predetermined positions on a basechip in which the embedded array is integrated, based on the system specification and a result of the step of logic designing. In the step of fabricating a mask pattern, a mask pattern for a master wafer is made in correspondence with a layout result of the step of designing layout. In the step of fabricating a master wafer, a master wafer is fabricated on the basechip using the mask pattern. In the step of designing interconnections, interconnections on the random logic block is designed using the result of the step of logic designing and the result of the step of designing layout. In the step of fabricating a metallization mask pattern, a metallization mask pattern is made using the result of the step of designing interconnections. In the step of metallizing, metallization is carried out on the master wafer using the metallization mask pattern. And, in the step of assembling, the external chip and the basechip are three-dimensionally assembled via a bump provided on the bump pad.
According to the fourth aspect, the embedded array which can be used as the base chip in a silicon on silicon-type MCM can be easily designed and manufactured. Therefore, an MCM using the embedded array can be easily manufactured.
A fifth aspect of the present invention relates to a storage medium, which can be read out by computer, storing data used in the manufacturing method of the three-dimensional MCM of the third aspect. In other words, the fifth aspect of the present invention is a storage medium, which can be read out by computer, storing data comprising a first data file and a second data file. Here, the first data file comprises: a verified macrocell cell information storage region; a bump pad cell information storage region for storing cell information of a bump pad for forming a three-dimensional multichip module by means of a bump. And, the second data file comprises a logic design result storage region for storing the result of logic design which has been conducted using the first data file.
When these types of data files are prepared, in the step of designing layout of the above third aspect, it is possible to automatically and easily determine the layout of the macrocells, the bump pad and the interconnections on the base chip, by using a first data file, storing cell information relating to the macrocells and cell information relating to the bump pad, and a second data file, storing the result of the logic design. Here, xe2x80x98storage mediumxe2x80x99 refers to a device capable of storing program such as, for instance, a semiconductor memory, a magnetic disk, an optical disk, an optical magnetic disk, a magnetic tape and the like. More specifically, it refers to a floppy disk, a CD-ROM, an MO disk, a cassette tape, an open-reel tape and such like.
A sixth aspect of the present invention relates to a storage medium, which can be read out by computer, storing data used in the manufacturing method of the three-dimensional MCM of the fourth aspect. In other words, the sixth aspect of the present invention is a storage medium, which can be read out by computer, storing data comprising a first data file and a second data file. Here, the first data file comprises: a cell information storage region for storing cell information of verified macrocells; a random logic block cell information storage region for storing cell information of a random logic block for executing functions of the macrocells; and a bump pad cell information storage region for storing cell information of a bump pad for forming a three-dimensional multichip module. And, the second data file comprises: a storage region for storing a floor plan of an embedded array; a layout storage region for storing layout of the macrocell, the random logic block and the bump pad using the first data file; and a logic design result storage region for storing the result of logic design which has been conducted, using the first data file.
When these types of data files are prepared, in the step of designing layout of the fourth aspect, it is possible to automatically and easily determine the layout of the macrocells, the random logic block and the bump pad on the base chip, by using a first data file, storing cell information relating to the macrocells and the random logic block as well as cell information relating to the bump pad, and a second data file, storing user data including the system specification. Furthermore, when the layout result of the step of designing layout is stored in the second data file in addition to the logic design result of the step of logic designing in the above fourth aspect, it is possible to use the stored layout result and the stored logic design result in the step of designing interconnections on the random logic block in the fourth aspect, whereby the metallization on the master wafer can be performed easily. Therefore, an embedded array which can be used as a base chip in a silicon on silicon-type MCM can be easily formed. Here, xe2x80x98storage mediumxe2x80x99 refers to a device capable of storing program such as, for instance, a semiconductor memory, a magnetic disk, an optical disk, an optical magnetic disk, a magnetic tape and the like. More specifically, it refers to a floppy disk, a CD-ROM, an MO disk, a cassette tape, an open-reel tape and such like.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.